270 lines
9.1 KiB
C++
270 lines
9.1 KiB
C++
// Copyright (c) 2011 The Chromium Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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// This file is an internal atomic implementation, use base/atomicops.h instead.
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#ifndef BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
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#define BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
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#include "base/base_export.h"
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// This struct is not part of the public API of this module; clients may not
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// use it. (However, it's exported via BASE_EXPORT because clients implicitly
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// do use it at link time by inlining these functions.)
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// Features of this x86. Values may not be correct before main() is run,
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// but are set conservatively.
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struct AtomicOps_x86CPUFeatureStruct {
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bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
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// after acquire compare-and-swap.
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bool has_sse2; // Processor has SSE2.
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};
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BASE_EXPORT extern struct AtomicOps_x86CPUFeatureStruct
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AtomicOps_Internalx86CPUFeatures;
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#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
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namespace base {
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namespace subtle {
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// 32-bit low-level operations on any platform.
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inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 prev;
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__asm__ __volatile__("lock; cmpxchgl %1,%2"
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: "=a" (prev)
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: "q" (new_value), "m" (*ptr), "0" (old_value)
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: "memory");
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return prev;
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}
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inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
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Atomic32 new_value) {
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__asm__ __volatile__("xchgl %1,%0" // The lock prefix is implicit for xchg.
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: "=r" (new_value)
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: "m" (*ptr), "0" (new_value)
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: "memory");
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return new_value; // Now it's the previous value.
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}
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inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 temp = increment;
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__asm__ __volatile__("lock; xaddl %0,%1"
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: "+r" (temp), "+m" (*ptr)
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: : "memory");
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// temp now holds the old value of *ptr
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return temp + increment;
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}
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inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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Atomic32 increment) {
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Atomic32 temp = increment;
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__asm__ __volatile__("lock; xaddl %0,%1"
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: "+r" (temp), "+m" (*ptr)
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: : "memory");
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// temp now holds the old value of *ptr
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return temp + increment;
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}
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inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return x;
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}
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inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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}
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inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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}
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#if defined(__x86_64__)
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// 64-bit implementations of memory barrier can be simpler, because it
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// "mfence" is guaranteed to exist.
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inline void MemoryBarrier() {
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__asm__ __volatile__("mfence" : : : "memory");
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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*ptr = value;
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MemoryBarrier();
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}
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#else
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inline void MemoryBarrier() {
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if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
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__asm__ __volatile__("mfence" : : : "memory");
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} else { // mfence is faster but not present on PIII
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Atomic32 x = 0;
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NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
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}
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
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*ptr = value;
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__asm__ __volatile__("mfence" : : : "memory");
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} else {
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NoBarrier_AtomicExchange(ptr, value);
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// acts as a barrier on PIII
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}
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}
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#endif
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inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
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ATOMICOPS_COMPILER_BARRIER();
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*ptr = value; // An x86 store acts as a release barrier.
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// See comments in Atomic64 version of Release_Store(), below.
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}
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inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
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return *ptr;
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}
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inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
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Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
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// See comments in Atomic64 version of Release_Store(), below.
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ATOMICOPS_COMPILER_BARRIER();
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return value;
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}
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inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
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MemoryBarrier();
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return *ptr;
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}
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#if defined(__x86_64__)
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// 64-bit low-level operations on 64-bit platform.
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inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 prev;
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__asm__ __volatile__("lock; cmpxchgq %1,%2"
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: "=a" (prev)
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: "q" (new_value), "m" (*ptr), "0" (old_value)
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: "memory");
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return prev;
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}
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inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
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Atomic64 new_value) {
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__asm__ __volatile__("xchgq %1,%0" // The lock prefix is implicit for xchg.
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: "=r" (new_value)
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: "m" (*ptr), "0" (new_value)
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: "memory");
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return new_value; // Now it's the previous value.
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}
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inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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Atomic64 temp = increment;
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__asm__ __volatile__("lock; xaddq %0,%1"
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: "+r" (temp), "+m" (*ptr)
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: : "memory");
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// temp now contains the previous value of *ptr
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return temp + increment;
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}
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inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
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Atomic64 increment) {
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Atomic64 temp = increment;
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__asm__ __volatile__("lock; xaddq %0,%1"
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: "+r" (temp), "+m" (*ptr)
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: : "memory");
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// temp now contains the previous value of *ptr
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return temp + increment;
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}
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inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
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*ptr = value;
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}
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inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
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*ptr = value;
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MemoryBarrier();
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}
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inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
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ATOMICOPS_COMPILER_BARRIER();
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*ptr = value; // An x86 store acts as a release barrier
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// for current AMD/Intel chips as of Jan 2008.
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// See also Acquire_Load(), below.
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// When new chips come out, check:
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// IA-32 Intel Architecture Software Developer's Manual, Volume 3:
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// System Programming Guide, Chatper 7: Multiple-processor management,
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// Section 7.2, Memory Ordering.
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// Last seen at:
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// http://developer.intel.com/design/pentium4/manuals/index_new.htm
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//
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// x86 stores/loads fail to act as barriers for a few instructions (clflush
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// maskmovdqu maskmovq movntdq movnti movntpd movntps movntq) but these are
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// not generated by the compiler, and are rare. Users of these instructions
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// need to know about cache behaviour in any case since all of these involve
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// either flushing cache lines or non-temporal cache hints.
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}
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inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
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return *ptr;
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}
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inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
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Atomic64 value = *ptr; // An x86 load acts as a acquire barrier,
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// for current AMD/Intel chips as of Jan 2008.
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// See also Release_Store(), above.
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ATOMICOPS_COMPILER_BARRIER();
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return value;
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}
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inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
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MemoryBarrier();
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return *ptr;
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}
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inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return x;
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}
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inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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}
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#endif // defined(__x86_64__)
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} // namespace base::subtle
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} // namespace base
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#undef ATOMICOPS_COMPILER_BARRIER
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#endif // BASE_ATOMICOPS_INTERNALS_X86_GCC_H_
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