254 lines
11 KiB
C
254 lines
11 KiB
C
/*
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* Copyright (c) 2012
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* MIPS Technologies, Inc., California.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the MIPS Technologies, Inc., nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Authors: Darko Laus (darko@mips.com)
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* Djordje Pesut (djordje@mips.com)
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* Mirjana Vulin (mvulin@mips.com)
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*
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* AAC Spectral Band Replication decoding functions optimized for MIPS
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**
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* @file
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* Reference: libavcodec/aacdec.c
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*/
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#ifndef AVCODEC_MIPS_AACDEC_MIPS_H
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#define AVCODEC_MIPS_AACDEC_MIPS_H
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#include "libavcodec/aac.h"
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#include "libavutil/mips/asmdefs.h"
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#if HAVE_INLINE_ASM && HAVE_MIPSFPU
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#if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
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static inline float *VMUL2_mips(float *dst, const float *v, unsigned idx,
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const float *scale)
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{
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float temp0, temp1, temp2;
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int temp3, temp4;
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float *ret;
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__asm__ volatile(
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"andi %[temp3], %[idx], 0x0F \n\t"
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"andi %[temp4], %[idx], 0xF0 \n\t"
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"sll %[temp3], %[temp3], 2 \n\t"
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"srl %[temp4], %[temp4], 2 \n\t"
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"lwc1 %[temp2], 0(%[scale]) \n\t"
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"lwxc1 %[temp0], %[temp3](%[v]) \n\t"
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"lwxc1 %[temp1], %[temp4](%[v]) \n\t"
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"mul.s %[temp0], %[temp0], %[temp2] \n\t"
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"mul.s %[temp1], %[temp1], %[temp2] \n\t"
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PTR_ADDIU "%[ret], %[dst], 8 \n\t"
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"swc1 %[temp0], 0(%[dst]) \n\t"
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"swc1 %[temp1], 4(%[dst]) \n\t"
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: [temp0]"=&f"(temp0), [temp1]"=&f"(temp1),
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[temp2]"=&f"(temp2), [temp3]"=&r"(temp3),
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[temp4]"=&r"(temp4), [ret]"=&r"(ret)
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: [idx]"r"(idx), [scale]"r"(scale), [v]"r"(v),
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[dst]"r"(dst)
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: "memory"
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);
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return ret;
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}
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static inline float *VMUL4_mips(float *dst, const float *v, unsigned idx,
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const float *scale)
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{
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int temp0, temp1, temp2, temp3;
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float temp4, temp5, temp6, temp7, temp8;
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float *ret;
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__asm__ volatile(
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"andi %[temp0], %[idx], 0x03 \n\t"
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"andi %[temp1], %[idx], 0x0C \n\t"
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"andi %[temp2], %[idx], 0x30 \n\t"
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"andi %[temp3], %[idx], 0xC0 \n\t"
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"sll %[temp0], %[temp0], 2 \n\t"
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"srl %[temp2], %[temp2], 2 \n\t"
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"srl %[temp3], %[temp3], 4 \n\t"
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"lwc1 %[temp4], 0(%[scale]) \n\t"
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"lwxc1 %[temp5], %[temp0](%[v]) \n\t"
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"lwxc1 %[temp6], %[temp1](%[v]) \n\t"
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"lwxc1 %[temp7], %[temp2](%[v]) \n\t"
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"lwxc1 %[temp8], %[temp3](%[v]) \n\t"
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"mul.s %[temp5], %[temp5], %[temp4] \n\t"
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"mul.s %[temp6], %[temp6], %[temp4] \n\t"
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"mul.s %[temp7], %[temp7], %[temp4] \n\t"
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"mul.s %[temp8], %[temp8], %[temp4] \n\t"
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PTR_ADDIU "%[ret], %[dst], 16 \n\t"
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"swc1 %[temp5], 0(%[dst]) \n\t"
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"swc1 %[temp6], 4(%[dst]) \n\t"
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"swc1 %[temp7], 8(%[dst]) \n\t"
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"swc1 %[temp8], 12(%[dst]) \n\t"
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: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1),
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[temp2]"=&r"(temp2), [temp3]"=&r"(temp3),
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[temp4]"=&f"(temp4), [temp5]"=&f"(temp5),
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[temp6]"=&f"(temp6), [temp7]"=&f"(temp7),
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[temp8]"=&f"(temp8), [ret]"=&r"(ret)
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: [idx]"r"(idx), [scale]"r"(scale), [v]"r"(v),
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[dst]"r"(dst)
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: "memory"
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);
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return ret;
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}
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static inline float *VMUL2S_mips(float *dst, const float *v, unsigned idx,
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unsigned sign, const float *scale)
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{
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int temp0, temp1, temp2, temp3, temp4, temp5;
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float temp6, temp7, temp8, temp9;
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float *ret;
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__asm__ volatile(
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"andi %[temp0], %[idx], 0x0F \n\t"
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"andi %[temp1], %[idx], 0xF0 \n\t"
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"lw %[temp4], 0(%[scale]) \n\t"
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"srl %[temp2], %[sign], 1 \n\t"
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"sll %[temp3], %[sign], 31 \n\t"
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"sll %[temp2], %[temp2], 31 \n\t"
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"sll %[temp0], %[temp0], 2 \n\t"
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"srl %[temp1], %[temp1], 2 \n\t"
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"lwxc1 %[temp8], %[temp0](%[v]) \n\t"
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"lwxc1 %[temp9], %[temp1](%[v]) \n\t"
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"xor %[temp5], %[temp4], %[temp2] \n\t"
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"xor %[temp4], %[temp4], %[temp3] \n\t"
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"mtc1 %[temp5], %[temp6] \n\t"
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"mtc1 %[temp4], %[temp7] \n\t"
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"mul.s %[temp8], %[temp8], %[temp6] \n\t"
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"mul.s %[temp9], %[temp9], %[temp7] \n\t"
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PTR_ADDIU "%[ret], %[dst], 8 \n\t"
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"swc1 %[temp8], 0(%[dst]) \n\t"
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"swc1 %[temp9], 4(%[dst]) \n\t"
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: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1),
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[temp2]"=&r"(temp2), [temp3]"=&r"(temp3),
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[temp4]"=&r"(temp4), [temp5]"=&r"(temp5),
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[temp6]"=&f"(temp6), [temp7]"=&f"(temp7),
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[temp8]"=&f"(temp8), [temp9]"=&f"(temp9),
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[ret]"=&r"(ret)
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: [idx]"r"(idx), [scale]"r"(scale), [v]"r"(v),
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[dst]"r"(dst), [sign]"r"(sign)
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: "memory"
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);
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return ret;
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}
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static inline float *VMUL4S_mips(float *dst, const float *v, unsigned idx,
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unsigned sign, const float *scale)
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{
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int temp0, temp1, temp2, temp3, temp4;
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float temp10, temp11, temp12, temp13, temp14, temp15, temp16, temp17;
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float *ret;
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unsigned int mask = 1U << 31;
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__asm__ volatile(
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"lw %[temp0], 0(%[scale]) \n\t"
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"andi %[temp1], %[idx], 0x03 \n\t"
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"andi %[temp2], %[idx], 0x0C \n\t"
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"andi %[temp3], %[idx], 0x30 \n\t"
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"andi %[temp4], %[idx], 0xC0 \n\t"
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"sll %[temp1], %[temp1], 2 \n\t"
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"srl %[temp3], %[temp3], 2 \n\t"
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"srl %[temp4], %[temp4], 4 \n\t"
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"lwxc1 %[temp10], %[temp1](%[v]) \n\t"
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"lwxc1 %[temp11], %[temp2](%[v]) \n\t"
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"lwxc1 %[temp12], %[temp3](%[v]) \n\t"
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"lwxc1 %[temp13], %[temp4](%[v]) \n\t"
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"and %[temp1], %[sign], %[mask] \n\t"
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"srl %[temp2], %[idx], 12 \n\t"
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"srl %[temp3], %[idx], 13 \n\t"
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"srl %[temp4], %[idx], 14 \n\t"
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"andi %[temp2], %[temp2], 1 \n\t"
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"andi %[temp3], %[temp3], 1 \n\t"
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"andi %[temp4], %[temp4], 1 \n\t"
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"sllv %[sign], %[sign], %[temp2] \n\t"
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"xor %[temp1], %[temp0], %[temp1] \n\t"
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"and %[temp2], %[sign], %[mask] \n\t"
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"mtc1 %[temp1], %[temp14] \n\t"
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"xor %[temp2], %[temp0], %[temp2] \n\t"
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"sllv %[sign], %[sign], %[temp3] \n\t"
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"mtc1 %[temp2], %[temp15] \n\t"
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"and %[temp3], %[sign], %[mask] \n\t"
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"sllv %[sign], %[sign], %[temp4] \n\t"
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"xor %[temp3], %[temp0], %[temp3] \n\t"
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"and %[temp4], %[sign], %[mask] \n\t"
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"mtc1 %[temp3], %[temp16] \n\t"
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"xor %[temp4], %[temp0], %[temp4] \n\t"
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"mtc1 %[temp4], %[temp17] \n\t"
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"mul.s %[temp10], %[temp10], %[temp14] \n\t"
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"mul.s %[temp11], %[temp11], %[temp15] \n\t"
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"mul.s %[temp12], %[temp12], %[temp16] \n\t"
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"mul.s %[temp13], %[temp13], %[temp17] \n\t"
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PTR_ADDIU "%[ret], %[dst], 16 \n\t"
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"swc1 %[temp10], 0(%[dst]) \n\t"
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"swc1 %[temp11], 4(%[dst]) \n\t"
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"swc1 %[temp12], 8(%[dst]) \n\t"
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"swc1 %[temp13], 12(%[dst]) \n\t"
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: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1),
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[temp2]"=&r"(temp2), [temp3]"=&r"(temp3),
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[temp4]"=&r"(temp4), [temp10]"=&f"(temp10),
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[temp11]"=&f"(temp11), [temp12]"=&f"(temp12),
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[temp13]"=&f"(temp13), [temp14]"=&f"(temp14),
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[temp15]"=&f"(temp15), [temp16]"=&f"(temp16),
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[temp17]"=&f"(temp17), [ret]"=&r"(ret),
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[sign]"+r"(sign)
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: [idx]"r"(idx), [scale]"r"(scale), [v]"r"(v),
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[dst]"r"(dst), [mask]"r"(mask)
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: "memory"
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);
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return ret;
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}
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#define VMUL2 VMUL2_mips
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#define VMUL4 VMUL4_mips
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#define VMUL2S VMUL2S_mips
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#define VMUL4S VMUL4S_mips
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#endif /* !HAVE_MIPS32R6 && !HAVE_MIPS64R6 */
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#endif /* HAVE_INLINE_ASM && HAVE_MIPSFPU */
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#endif /* AVCODEC_MIPS_AACDEC_MIPS_H */
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